..:: Introduction ::..
When the original Pentium 4 microprocessor debuted several years ago, it was their first x86 microprocessor built from the ground up to debut since the days of the Pentium Pro. From the times of the Pentium Pro onward to that of the Pentium III, all of the processor generations had been built on an ever improved P6 architecture. With the end of the Pentium III and the beginning of the Pentium 4, Intel moved on towards their NetBurst architecture scheme. At first, many did not particularly care for some of the NetBurst architecture’s features, those that many enthusiasts viewed as the weak points. The main aspect that was viewed as an achilles heel for the Pentium 4’s microarchitecture was the length of the pipeline, twenty stages, double that of the Pentium III. Well, “Prescott” keeps on trucking along this line of deeper piplines as it features a massive thirty one stage pipeline!
As some of you may, or may not know, in the world of superscalar microprocessor architecture, one way to increase the clock frequency capabilities of a given microarchitecture is to increase the pipeline length. By increasing the length of the pipeline, executions can be broken up into separate, smaller steps which allow for easier scaling of the architecture, and therefore overall speed (MHz) of the microprocessor. The downsides to increasing the pipeline length are that the processor has a lessened IPC, or instructions per clock, capability. AMD, Intel’s main competitor has used their IPC rating as a way to set apart their offerings from the likes of Intel. Even AMD’s latest microprocessors based off of their x86-64 microarchitecture do not feature a pipeline as deep as that of Intel’s Pentium 4. The main downside to a deeper pipeline deals with branch misprediction. When a branch is mispredicted, the entire pipeline must then be flushed, and all of the data that was flowing through must restart from scratch. This induces performance killing penalties that can hamper the true capability of the processor. As pipelines are deepened, there is an ever increasing need for a more accurate branch prediction algorithm to avoid such problems, and we’ll soon see how Intel has tackled the problem of branch prediction.
As word of Intel’s “Prescott” core grew, many began to believe that “Northwood” was the end of the road for the Pentium 4, and “Prescott” would bring in the beginning generations of the Pentium V, or next generation processor depending on Intel’s naming scheme. After details of the core enhancements began to become publicly available as time went on, it was seen that “Prescott” would not bring an end to the Pentium 4 line, rather it would be yet another tweaked version of the core, with enhancements made to the microarchitecture, along with several “standard” enhancements such as an increase in the size of the on-die L2 cache. Many, including myself, initially believed that the 3.20GHz mark would be the end of the Pentium 4 “Northwood” core, although today, along with the release of several “Prescott” and “EE” processors, Intel has released a 3.40GHz “Northwood” core processor. In our review of the 3.20GHz “Northwood,” we found that Intel did seem to have enough frequency room to work with to create a 3.40GHz version, although we did not believe that they would do so, and obviously were incorrect. Today, we will be examining the various enhancements that Intel has made to with the “Prescott” core, and bring to rest some of the rumors about performance, microarchitecture changes, and more that have been floating around the internet.