Intel Extreme Edition 955

..:: Introduction ::..

It seems like it was just yesterday that we were sitting here discussing Intel’s move to the 90nm manufacturing process and the “Prescott” core, yet today we have the first chip in our hands built using the latest 65nm process, the “Presler” Extreme Edition 955. The move to 65nm comes after a rather problematic transition to 90nm. With the “Prescott” core, Intel adopted a huge 31 stage processing pipeline, up from the 20 stages that were previously seen across the Pentium 4 line.

Surprisingly, the “Prescott” core fared well against the 20 stage “Northwood” on a clock-for-clock basis due to some of the architectural changes. The Achilles heel of both the “Prescott”, and eventually the “Prescott 2”, core was and still is, heat. These cores pump out tremendous amounts of heat to go along with their light dimming power consumption. Well, maybe not quite to that level, but nevertheless under both idle and load conditions these cores gobbled up power.

The 31 stage pipeline can be thanked somewhat for causing the increase in power consumption, as well as heat. One of the main trade-offs of a high frequency, deeply pipelined processor is that it’s undoubtedly going to gobble up power. In the future “Conroe” will cut the current pipeline length to 14 stages, something that will certainly help Intel with power consumption.

With the later versions of the 90nm “Prescott” core, Intel took on the issue of power consumption by implementing thermal controls and dynamic clocking into the Pentium 4 line. We’ve seen this in action and it works like a charm, taking our 3.4GHz processor down to 2.8GHz when under lower load conditions. This technology helped lower the power consumption, but alone it wasn’t enough to make up the huge difference between the Pentium 4 and its leading competition from AMD.

With the advent of the “Smithfield” core, we saw similar heat and power consumption issues arise now that we had not one, but two processing cores running side by side. With the addition of EIST on the Extreme Edition and Pentium D models beyond the 820, the processors would dynamically lower the multiplier to 14x when the system was running under a low load state. If full processing power was required, then they’d quickly ramp back up to their full multiplier setting allowing for full utilization. The problem of power consumption will be better addressed in the future with “Conroe” variants and the un-named architecture.

For now, we’re seeing the launch of the first 65nm cores, code-named “Cedar Mill” and “Presler”. The “Cedar Mill” processors will be launched in the future and are quite simply the single core versions of the “Presler” dual core processors. With the move to 65nm, we should, in theory, see at least a decent drop in power consumption between the “Smithfield” and “Presler” cores. “Presler” and “Smithfield” differ in that “Presler” features two separate cores that are interconnected, while with “Smithfield” both of the processing cores were on one piece of silicon. Architecturally, they are one in the same, with a little shrinkage.



 
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