Intel EM64T Technology - Page 3

..:: Register Modifications - SSE ::..

With regards to the SSE registers, there are eight available 128-bit registers (XMM0 - XMM7) while operating under legacy or compatibility modes, while Intel has added an additional eight 128-bit SSE registers (XMM7 - XMM15) for 64-bit operation. Access to these new SSE registers is allowed only on an instruction-by-instruction basis, with the REX opcode prefix. No matter what operating mode, all of the registers can be used with SSE, SSE2, and SSE3.

..:: Register Modifications - System Registers ::..

Figure 3.

Several major additions, as well as modifications have come to several of the system registers to allow for support of EM64T. One of the internal Model Specific Registers, or MSR, within the IA-32e architecture is the Extended Feature Enable MSR. This MSR contains the bits for controlling EM64T features, as well as for enabling or disabling the EM64T Technology.

Within the E.F.E. MSR register, the various bits are broken into different subsets depending on their function. For example, bit 0 enables control of the SYSCALL and SYSRET 64-bit instructions which are only available when operating under 64-bit mode. These are two new instructions that have been added to the instruction set for EM64T. Two of the remaining bits within this register also deal with support for EM64T. Bit 8 controls whether or the processor can switch to IA-32e mode, while read-only bit 10 can be used to determine when IA-32e mode or compatibility mode is active. It can be determined which of these two modes the processor is in depending upon the value currently stored in the code segment descriptor.

In the EM64T architecture, the various control registers have all been expanded to 64-bits wide. The MOV CRn instruction, where n corresponds to the control register’s number, can read or write 64 bits to these control registers. While operating in either compatibility or legacy modes, writes to these control registers results in the upper 32 bits being filled with zero’s, while the reads return only the lower 32 bits. Under 64-bit mode two of the control registers, CR0 and CR4, have reserved space in their upper 32 bits so these must also be written with zero’s. CR2 offers support for writing to all 64-bits, while CR3 has reserved bits from 51:40.

There is also a new control register that have been added to the EM64T architecture, CR8. This register is defined as the task priority register. This register is the new interrupt control priority mechanism that was discussed earlier. The operating system can use this register to control whether or not to allow any external interrupts to interrupt the processor. The way the operating system can do this is by loading the task priority register with the value associated with the highest priority level interrupt to be blocked. Under the APIC specifications, there are fifteen interrupt priority classes ranging from 1, the lowest, to 15, the highest. If the task priority register is loaded with the value for 6 via the operating system, then all interrupts with a priority of 6 or lower would be blocked.

Finally, the debug registers have also been extended to 64-bits wide. As with the MOV CRn instruction, the MOV DRn instructions read or write to all 64 register bits. The other similarity between these two instruction sets is the way they handle 32-bit operands. The MOV DRn instructions also write zero’s to the upper 32 bits of the register, and reads from the lower 32 bits. Several of the debug registers also have reserved bits, such as the upper 32 bits of the DR6 and DR7 registers.