In order to achieve the most efficient return current, the designer must do two things. First off, the designer must attempt to maintain a single constant return path as much as possible. Secondly, the designer must make sure that both the source of the signal and the destination of the signal both tie into the return plane’s voltage rail. In order to illustrate an example of this, let’s discuss the 1.80V DDR-II system bus hat the new chipsets from Intel, and other upcoming manufacturers will utilize.

     First off, we need to determine both the source and the destination for the signal. In the case of the DDR-II bus, we’ll take the driver within the chipset to be the source of the signal, while the bus recovery inside the DRAM device mounted on the DIMM’s PCB will be the destination. Now that we have our source and destination, let’s take a look at the actual interconnect and power plane. As the interconnect breaks away from the chipset, it will travel a pre-defined distance, called “tuning” which I’ll be covering in a minute, to a given pin on the DIMM socket, and up the DIMM’s PCB to the DDR-II device. Underneath this data interconnect, there exists a 1.80V power plane.

     From a designer’s standpoint, they could choose to do something called “flooding,” basically creating a large plane of copper to power the DDR bus and for the return currents to flow along. From a power delivery point of view, this would be great because the designer would have a large plate of copper to use to deliver power to the chipset power pins, and the DIMM’s power pins. One small problem that arises here is that in reality, it isn’t this simple. If you were to take a look at the various layers of a DIMM’s PCB, you’d see that unlike our motherboard, the signaling layer is actually placed above a ground layer. If the motherboard designer chooses to route the interconnect traces over the 1.80V power plane, called “power referencing”, then it will have problems when it hits the DIMM PCB which is referenced to ground. The return current won’t simply stop when this mismatch happens, nor will it simply “jump” from one layer to the other. The return current will in effect find a way to change from the 1.80V power layer on the motherboard to the ground layer of the DIMM. Because this has to happen, the signal will experience some degradation issues. If there are multiple signals taking part in this process at once, you can run into some very serious problems.

     In order to avoid such problems, the motherboard designer has to rethink the way they want to lay out these items. A better layout would be to run the interconnect over a second layer ground plane instead of the 1.80V power plane. The designers can embed a ground plane under the DDR-II bus just as easily as a power plane, and that would give the return current a uniform path to travel when returning from the destination to the source. Using the ground plane as the second layer instead of power makes things a little more interesting when it comes to power delivery which is why you’ll be able to see some interesting “shapes” on the top and bottom layers that are used for the power delivery.